1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel that can minimize the power consumption required for driving the plasma display panel.
2. Discussion of the Related Art
A plasma display panel (hereinafter referred to as PDP) is a device that displays pictures including texts or graphics by effecting luminescence of phosphors by ultraviolet (UV) rays generated during the discharge of an inert mixed gas (for instance, He+Xe or Ne+Xe).
Such a PDP has the advantage that it can be easily formed into a thin film and large-sized, and recently, with the technical development, it can provide a greatly improved picture quality.
A typical PDP, as shown in FIG. 1, has three electrodes, and is driven by an AC voltage. This is called an AC surface discharge type PDP.
In this AC surface discharge type PDP having three electrodes, wall charge is accumulated on its surface during the discharging operation, and the electrodes are protected from sputtering generated due to the discharging operation. Thus, it has the advantages of a low-voltage drive and a long lifetime.
FIG. 1 is a perspective view of a discharge cell structure of a conventional AC surface discharge type PDP having three electrodes.
Referring to FIG. 1, the discharge cell of the three-electrode AC surface discharge type PDP is provided with a scan electrode 12Y and a sustain electrode 12Z formed on a front substrate 10, and an address electrode 20X formed on a back substrate 18.
On the front substrate 10 where the scan electrode 12Y and the sustain electrode 12Z are formed in lines are laminated a front dielectric layer 14 and a protective layer 16. On the front dielectric layer 14 is accumulated the wall charge generated during the plasma discharge.
The protective layer 16 prevents the damage of the front dielectric layer 14 due to the sputtering generated during the plasma discharge, and heightens the emission efficiency of secondary electrons. As the protective layer 16 is typically used a magnesium oxide (MgO).
On the back substrate 18 where the address electrode 20Z is formed are formed a back dielectric layer 22 and a barrier rib 24. On surfaces of the back dielectric layer and the barrier rib 24 is formed phosphors 26.
The address electrode 20X is formed in an intersectional direction of the scan electrode 12Y and the sustain electrode 12Z.
The barrier rib 24 is formed in lines with the address electrode 20X, and prevents the leakage of the ultraviolet rays and visible rays generated by the discharge to an adjacent discharge cell.
The phosphors 26 are excited by the ultraviolet rays generated during the plasma discharge to generate one among visible rays of red, green, and blue. In a discharge space provided among the two substrates 10 and 18 and the barrier rib 24 is injected an inert gas for gas discharge.
The discharge cells as described above are arranged in the form of a matrix as shown in FIG. 2.
As shown in FIG. 2, in one discharge cell 1, scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm are arrange in parallel, and discharge cells are provided at the intersection portions of the two parallel electrode lines Y1 to Ym, and Z1 to Zm and the address electrode lines X1 to Xn, respectively.
The scan electrode lines Y1 to Ym are sequentially driven, and the sustain electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven, being divided into odd lines and even lines.
In this AC surface discharge type PDP having three electrodes, a driving time for representing a specified gray scale with respect to a frame is separated into a plurality of sub-fields. For a sub-field duration, the luminescence is performed with its frequency proportioned to a weight of the video data to perform the representation of the gray scale.
FIG. 3 is a view illustrating an example of a frame structure according to the driving of the conventional PDP.
Referring to FIG. 3, one frame according to the driving of the AC surface discharge type PDP having three electrodes is divided into 12 sub-fields SF1 to SF12 in time. Specifically, one frame duration in the respective discharge cell 1 is divided into selective write type sub-fields SF1 to SF6 and selective erase type sub-fields SF7 to SF12.
The selective write type sub-fields represent a low gray scale by maintaining the discharge of the discharge cells selected and turned on, and the selective erase type sub-fields represent a high gray scale by turning off the cells which were turned on in the last selective write type sub-field among the selective write type sub-fields.
The first sub-field SF1 is divided into a reset period for initializing the whole picture, a selective write address period for turning on the selected discharge cells, a sustain period for keeping the sustain discharge of the discharge cells selected by an address discharge, and an erase period for erasing the sustain discharge.
The second to fifth sub-fields SF2 to SF5 are each divided into a selective write address period, a sustain period, and an erase period.
Also, the sixth sub-field SF6 is divided into a selective write address period and a sustain period.
Specifically, in the first to sixth sub-fields SF1 to SF6, the selective write address period and the erase period are determined in the same ratio. On the contrary, the sustain period is given in the ratio of 2N (where, N=0, 1, 2, 3, . . . , 7) with different time weights in the respective sub-fields SF1 to SF6. That is, the sustain period is increasingly given in the ratio of 1:2:4:8:16:32:64:128 in the first to eighth sub-fields SF1 to SF8.
The next seventh to twelfth sub-fields SF7 to SF12 are each divided into a selective erase address period for turning off the selected discharge cells without a period for writing the whole picture, and a sustain period for effecting the sustain discharge of the discharge cells except for the discharge cells selected by the address discharge.
In the seventh to twelfth sub-fields SF7 to SF12, the selective erase address period and the sustain period are determined in the same ratio.
Especially, the sustain period of the seventh to twelfth sub-fields SF7 to SF12 is determined to having the same luminance relative ratio as the sixth sub-field SF6.
The seventh to twelfth sub-fields SF7 to SF12 are driven by the selective erasing method, and thus the previous sub-field should be necessarily in a turned-on state so as to be able to turn off the unnecessary discharge cells whenever the respective sub-fields continue.
For example, in order for the seventh sub-field SF7 to be turned on, the sixth sub-field SF6 that is driven by the selective erasing method should be turned on.
After the sixth sub-field SF6 is turned on as above, the seventh to twelfth sub-fields SF7 to SF12 turn off the unnecessary discharge cells.
In order to utilize the selective erase sub-fields (ESF) SF7 to SF12 of the selective erasing type, the discharge cells which were turned on at the sixth sub-field SF6 that is the last selective write sub-field (WSF) should be kept in a turned-on state by the sustain discharge.
Accordingly, the seventh sub-field SF7 does not need a separate writing discharge for the selective erase addressing. Also, the eighth to twelfth sub-fields SF8 to SF12 selectively turn off the cells of the turned-on state at the previous sub-field without writing of the whole picture.
FIG. 4 is a waveform diagram illustrating an example of driving waveforms according to the PDP driving in the frame of FIG. 3.
Referring to FIG. 4, for a reset period of a first selective write sub-field SW1, a reset pulse RP of a ramp-up waveform is supplied to the scan electrode lines Y in a set-up period, and then a reset pulse −RP of a ramp-down waveform is supplied to the scan electrode lines Y in a set-down period.
The reset pulse −RP of the ramp-down waveform descends to a negative (−) scan reference voltage −Vw. At the time point when the reset pulse −RP of the ramp-down waveform is supplied, a positive (+) scan DC voltage DCSC starts to be supplied to the sustain electrode lines Z.
For the address period of the first selective write sub-field SW1, a negative (−) selective write scan pulse −SWSP is supplied to the scan electrode lines Y while the positive (+) scan DC voltage DCSC is supplied to the sustain electrode lines Z, and a positive (+) selective write data pulse SWDP that is synchronized with the negative (−) selective write scan pulse −SWSP is supplied to the address electrode lines X.
In order to produce the sustain discharge with respect to the discharge cells selected by the address discharge, sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z during the sustain period of the first selective write sub-field SW1.
Also, at the end time point of a second selective write sub-field SW2, an erase pulse EP for erasing the sustain discharge is supplied to the scan electrode lines Y.
The reset period of the next selective erase sub-fields SE1,SE2, . . . is omitted as described above, and the address period starts directly.
For the address period of the selective erase sub-fields SE1,SE2, . . . , selective erase pulses SESP and SEDP for turning off the discharge cells are supplied to the scan electrode lines Y and the address electrode lines X, respectively. In more detail, a negative (−) selective erase scan pulse −SESP is supplied to the scan electrode lines Y, and a positive (+) selective data pulse SEDP that is synchronized with the negative selective erase scan pulse −SESP is supplied to the address electrode lines X. Here, the selective erase scan pulse −SESP is supplied with a selective erase scan voltage level −Ve that is higher than the scan reference voltage −Vw.
For the sustain period of the selective erase sub-fields SE1,SE2, . . . , the sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z so that the sustain discharge is produced with respect to the discharge cells which are not turned off by the address discharge.
In case that the following sub-field is the selective erase field SE, the sustain pulse SUSPy having a relatively large pulse width is supplied to the scan electrode lines Y at the end time point of the present selective erase sub-field SE.
In the last selective erase sub-field, an erase pulse EP and a ramp pulse are supplied to the scan electrode lines Y and the sustain electrode lines Z. Accordingly, the sustain discharge of the discharge cells of the turned-off state is erased. At this time, the next sub-field of the last selective erase sub-field will be the selective write sub-field SW.
FIGS. 5A to 5C are views illustrating the wall charge formed in a reset period of a selective write sub-field of FIG. 4, and especially the wall charge generated by a ramp pulse applied in a reset period of the first sub-field SF1 in FIG. 4.
The wall charge illustrated in FIG. 5A is caused by the ramp-up waveform (RP; A) applied in the reset period. If the reset pulse of the ramp-up waveform (RP; A) is applied in the reset period of the first sub-field SF1, the wall charge is accumulated over a specified amount on the scan electrode Y and the sustain electrode Z of the whole panel.
The wall charge illustrated in FIG. 5B is caused by the ramp-down waveform (−RP; B) applied in the reset period. If the reset pulse of the ramp-down waveform (−RP; B) is applied in the reset period of the first sub-field SF1, the wall charge accumulated on the scan electrode Y and the sustain electrode Z is removed to some extent.
Thereafter, if the reset period of the first sub-field SF1 ends, the ramp-down waveform (−RP; B) becomes the scan reference voltage −Vw, and the wall charge will be as shown in FIG. 5C.
As shown in FIGS. 5A to 5C, since in the reset period of the first sub-field SF1, the wall charge is accumulated on the address electrode X as well as on the scan electrode Y and the sustain electrode Z, the address electrode X can be driven by a voltage that is lower than the voltage level of the data pulse applied to the address electrode X as much as the wall charge in the first sub-field SF1.
However, after the second sub-field SF2, the driving conditions of the sub-fields are different.
That is, in the second sub-field SF2, there are the discharge cells of the turned-on state and the discharge cells of the turned-off state in the previous sub-field, and when the conditions of the wall charge accumulated on the respective electrodes in the two kinds of discharge cells separated before the address period of the sub-field become the same, the driving of a new sub-field starts again.
Accordingly, a method is used for lowering the positive (+) wall charge accumulated on the address electrode X of the discharge cells of the turned-off state to the voltage level of the wall charge of the discharge cells of the turned-on state. This is achieved using the reset pulse of the ramp-down waveform that descends to the negative (−) voltage level.
In other words, the general driving of the PDP has been performed using the ramp waveform for each sub-field. That is, the whole panel is initialized using the reset pulse of the high ramp waveform irrespective of the discharge cells of the turned-on state and the discharge cells of the turned-off state after the sustain discharge.
However, according to the driving method according to the driving waveform of FIG. 4, a high contrast characteristic is obtained by using the driving method that matches the conditions of the discharge cells of the turned-on state and the discharge cells of the turned-off state without using the reset pulse of the ramp waveform that deteriorates the contrast characteristic.
According to this driving method, however, since the voltage level of the data pulse is lowered as much as the wall charge only in the first sub-field SF1, the voltage level of the positive (+) wall charge accumulated on the address electrode X is lowered after the second sub-field SF2, and this causes the data driving voltage (voltage level of the data pulse) to be heightened.
FIG. 6 is a waveform diagram illustrating another example of driving waveforms according to the PDP driving in the frame of FIG. 3.
Referring to FIG. 6, all the sub-fields SW1 to SW12 of one frame are selective write sub-fields.
For a reset period of a selective write sub-field SW, a reset pulse RP of a ramp-up waveform is supplied to the scan electrode lines Y in a set-up period, and then a reset pulse −RP of a ramp-down waveform is supplied to the scan electrode lines Y in a set-down period.
At this time, the reset pulse −RP of the ramp-down waveform descends to a negative (−) scan reference voltage −Vw. At the time point when the reset pulse −RP of the ramp-down waveform is supplied, a positive (+) scan DC voltage DCSC starts to be supplied to the sustain electrode lines Z. This is for reducing the wall charge formed on the respective electrodes.
For the address period of the selective write sub-field SW1, a negative (−) selective write scan pulse −SWSP is supplied to the scan electrode lines Y while the positive (+) scan DC voltage DCSC is supplied to the sustain electrode lines Z, and a positive (+) selective write data pulse SWDP that is synchronized with the negative (−) selective write scan pulse −SWSP is supplied to the address electrode lines X.
In order to produce the sustain discharge with respect to the discharge cells selected by the address discharge, sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z during the sustain period of the selective write sub-field SW.
Also, at the end time point of the selective write sub-field SW, an erase pulse EP for erasing the sustain discharge is supplied to the scan electrode lines Y.
In the PDP driving according to FIG. 6, the PDP driving becomes stable as the number of reset pulses of the ramp waveform becomes larger. However, it has the drawback in that it deteriorates the contrast characteristic.
Also, in the conventional PDP driving according to FIG. 6, since the reset pulse −RP of the ramp-down waveform descends to the negative (−) scan reference voltage −Vw, the positive (+) selective write data pulse SWDP applied in synchronization with the negative (−) selective write scan pulse −SWSP in the address period should be kept in a high voltage level. In other words, it has the drawback in that the data driving voltage (i.e., voltage level of the data pulse) becomes heightened.